HBM4

HBM4 is the high-bandwidth memory (HBM) generation that follows HBM3 and HBM3E: the stacked DRAM that AI accelerators carry in the same package as the processor. Micron describes HBM as a 3D stacked DRAM architecture whose through-silicon via (TSV) connections give it higher bandwidth at lower power than other memory types.¹ JEDEC, the microelectronics standards body, published HBM4 as JESD270-4 on April 16, 2025, calling it an evolutionary step beyond its previous HBM3 standard.² It runs at up to 8 Gb/s per pin across a 2,048-bit interface, for up to 2 TB/s per stack; doubles the independent channels per stack from HBM3’s 16 to 32; and supports 4-, 8-, 12- and 16-high stacks of 24 Gb or 32 Gb dies, for up to 64 GB in a 16-high stack of 32 Gb dies.²

The memory makers moved to volume in 2026. SK hynix says it began mass shipments of HBM4 in the second quarter of 2026 and will ramp production in the second half;³ Samsung says it scaled up HBM4 sales in the same quarter and shipped the industry’s first HBM4E samples, a claim that is its own.⁴ Counterpoint Research estimated in September 2026 that most HBM revenue still came from HBM3E, with HBM4 shipments expected to become visible in earnest from the second half of 2026,⁵ and TrendForce cites a growing share of higher-priced HBM4 among the reasons it projects HBM’s blended average selling price to rise 121% in 2027.⁶ Those figures are in The Memory Crunch, by the Numbers.

In AI Accelerators With the Most HBM per Chip (October 2026), NVIDIA’s Rubin GPU is the only shipping accelerator with HBM4: 288 GB at 22 TB/s per GPU in HGX Rubin NVL8, by NVIDIA’s account.⁷ AMD’s Instinct MI455X, launched July 23, 2026 but not yet confirmed as shipping, lists 432 GB of HBM4 in 12 stacks at 23.3 TB/s.⁸